Research activity at Algorithms and Logic Synthesis (ALOS) Lab is mainly focused on the study and description of algorithms and models for logic synthesis and testing of integrated circuits. In particular, the research activity regards area and delay minimization, low power synthesis, and testability properties of minimized circuits.

Main research topics:

  • Algorithms for Logic Synthesis and Optimization
  • Multilevel and Multivalued Logic Networks Minimization
  • Testing and Testability of Boolean Circuits
  • Low Power Circuits and Green Computing
  • Efficient Minimization of Regular and Symmetric Boolean Functions
  • Boolean Function Decomposition and Factoring
  • Compact Data Structures for Logic Synthesis
  • Error Resilient Algorithms and Data Structures
  • Synthesis Methods for Synthetic Biology

Each year, from 2005, ALOS Lab coordinates and organizes the National Workshop on Logic Synthesis, which is a forum for exchanging ideas and discussing research results in the areas of logic synthesis and verification.